FIG. 1 shows one known implementation of a modular SST circuit topology for Low Voltage (LV) side grid tied application. Briefly, a SST typically comprises a HV side 110, a LV side 130 and a DAB 120 between the HV 110 and LV 130. Returning back to FIG. 1, the HV side 110 Neutral Point Clamp (NPC) 3-level Cascaded H-Bridge (CHB) converter are connected to single phase HV side Alternating Current (AC) voltage source. For each individual DAB module, its HV side NPC half bridge DC-AC converter is connected through a HV side DC bus to NPC CHB module. The modular DAB LV side 2-level full bridge AC-DC converters are connected through a common LV DC bus to a LV AC grid tied three-phase inverter. This NPC CHB 3-level SST circuit configuration supports bi-directional power flow between HV and LV AC grid sources with less number of High Frequency (HF) transformers and power devices. As the last solution for capacitor over voltage protection of this SST circuit, an individual chopper discharging circuit is connected to each DC bus capacitor. In normal SST operation, the chopper discharging circuit should not be activated in normal power regulation. For this NPC CHB SST circuit topology, it is required that the NPC top/bottom capacitor voltage balancing control to be implemented in NPC CHB controller to avoid unsymmetrical HF transformer current generated by the DAB NPC capacitor voltage balancing control. Module level voltage balancing control is also required for this NPC CHB SST circuit topology to minimize the NPC CHB circuit total DC bus voltage variation.
FIG. 2 shows another popular modular SST circuit topology composed of 2-level full bridge converter for both CHB and DAB. For the same HV side 110 grid voltage level and CHB power device voltage rating, 2-level full bridge SST circuit topology requires more levels of CHB and DAB modules and more number of HF transformers. Similar to the SST NPC CHB circuit topology, a chopper discharging circuit is connected to each capacitor as the last solution for SST DC bus over voltage protection. Module level HV side DC bus voltage balancing control is required for this SST circuit topology to minimize the CHB DC bus voltage variation.
In SST system, the control objective of LV side 130 DC-AC inverter is to regulate the bi-direction of active power flow of the entire SST system around its target value and to regulate the bi-direction reactive power output to LV side grid around its reference value. The control objective of HV side CHB converter is to regulate the total HV DC bus voltage around its target value with fast dynamic response with evenly distributed voltage output among each CHB module. The control objective of modular DAB DC-DC converter is to regulate the LV DC bus voltage around its target value with fast dynamic response.
In the SST converter system, module level HV side 110 DC bus voltage balancing could be affected by the imperfect HV side CHB control performance due to the non-ideal power switching operation, the practical HV side DC bus capacitance variation, and the imperfect DAB current/power distribution performance due to DAB module-to-module circuit parameter variations. The unbalanced HV side DC bus voltage will cause the capacitor or power device overvoltage in the CHB and DAB circuit and trigger the SST overvoltage protection.
Conventionally, the modular CHB converter voltage balancing control is generally applied for SST HV side DC bus voltage balancing control. The often cited limitation of this type of voltage balancing solution is that it requires significant amount of reactive current flow in the CHB converter for the voltage balancing algorithm to work properly in light load condition. Another disadvantage of CHB voltage balancing algorithm is that the grid current is slightly distorted due to PWM modulation signal injection from the voltage balancing algorithm.
FIGS. 3a and 3b show the conventional module level H-bridge voltage balancing control for HV side 110 CHB converter in regular power regulation for the 2-level full bridge CHB and DAB SST circuit topology shown in FIG. 2. The H-bridge voltage balancing scheme shown in FIG. 3a is responsible for module level HV DC bus voltage balancing control. The capacitor voltage error is regulated by a PI controller to generate d-axis voltage reference compensation signal which is added to the fundamental d-axis voltage reference generated by the d-axis current regulation. In this configuration, if the active power unbalance among the DAB modules is too large, the CHB voltage balancing algorithm will not be able to maintain the balanced HV DC bus voltage. FIG. 3b shows the power balance control scheme implemented in DAB controller to help to reduce the active power unbalance generated by the DAB module circuit parameter variation so that the conventional CHB voltage balancing algorithm can work more effectively.
The disadvantage of the power balancing control scheme based on that shown in FIGS. 3a and 3b is that the CHB voltage balancing control is only applied as inputs to the d-axis voltages. This type of voltage balancing control is not effective in the start-up process of SST when only CHB converter control is activated and when CHB is operating around zero power condition. For this power balancing control scheme, reactive current in CHB cannot help to improve the voltage balancing performance because q-axis voltage reference is not affected by the voltage balancing component. Another disadvantage of this SST power voltage balancing control scheme is that the DAB power balancing control is a feedforward control to mitigate the DAB control sensitivity to circuit parameter variations, and CHB voltage balancing control needs to be activated in the entire operation range of SST in normal power regulation.
An enhanced CHB capacitor voltage balancing scheme is proposed as shown in FIG. 4 with DC bus voltage error proportional control method which utilizes the magnitude normalized grid current to change the direction of voltage balancing PWM modulation injection signal. The DC bus voltage error passes through a moving average filter (MAF) as one input for voltage balancing control. The peak value of grid current is computed from root mean square (RMS) value of the grid current. The magnitude normalized grid current is computed by dividing the grid current signal by its peak value. This CHB voltage balancing control method can be applied for individual NPC CHB module top/bottom voltage balancing control as well as SST module level voltage balancing control. When applied in SST converter system, the CHB voltage balancing control performance will be improved by injecting certain amount of reactive current in the CHB control at zero power or light load condition. However, the disadvantage of this CHB voltage balancing control is that the load/power dynamic response from the DAB may vary.
FIG. 5 shows a SST HV DC bus voltage balancing control which is implemented in single voltage loop DAB control system by directly generating the phase shift angle adjustment signals for each individual DAB. However, the disadvantage of this DAB control based voltage balancing control scheme is that single voltage loop DAB control is slow in load/power dynamic response and very sensitive to the DAB parameter variations. This creates extra disturbance to the PI controller in the load/power dynamic transition period. The dynamic performance of this DAB voltage balancing control is not reliable.
Hence, those skilled in the art are striving to provide an improved method of balancing the Direct Current (DC) bus capacitor voltage at the High Voltage (HV) side of a SST system.